Closeness metrics for system-level functional partitioning
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Rate derivation and its applications to reactive, real-time embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System synthesis for multiprocessor embedded applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
System-level abstraction semantics
Proceedings of the 15th international symposium on System Synthesis
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems
Proceedings of the tenth international symposium on Hardware/software codesign
Targeting Tiled Architectures in Design Exploration
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Journal of Embedded Computing - Cache exploitation in embedded systems
A priori implementation effort estimation for hardware design based on independent path analysis
EURASIP Journal on Embedded Systems - Operating System Support for Embedded Real-Time Applications
| Hi-index | 0.00 |
Designing embedded systems is a challenging task during which wrong choices can lead to extremely costly re-design loops, especially when these wrong choices are made during the algorithm specification and the mapping over the selected architecture. In this paper we propose a high-level approach for design space exploration, using a usual standard language as input. More precisely we present the two first steps of the Design Trotter framework: (i) the specification step and its underlying internal model (HCDFG: Hierarchical and Control Data Flow Graph) and (ii) the characterization step which takes place very early in the design flow. Indeed, once transformed into our internal representation, the specification is rapidly and automatically characterized and explored at the algorithmic level. The framework provides the designer with metrics so that he can evaluate, very early in the design process, the impact of algorithmic choices on resource requirements in terms of processing, control, memory bandwidth and potential parallelism at different levels of granularity. The overall aim of our approach is to improve the algorithm/architecture matching that sorely influences the implementation efficiency in terms of silicon area, performances and energy consumption. We give examples which illustrate how designers can refer to the outcomes of the Design Trotter framework in order to select or build suitable architectures for specific applications.