Background memory area estimation for multidimensional signal processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A flexible code generation framework for the design of application specific programmable processors
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Aspects of system-level design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems
Proceedings of the tenth international symposium on Hardware/software codesign
A VLSI System Perspective for Microprocessors Beyond 90nm
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Benefits and challenges for platform-based design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of VLSI Signal Processing Systems
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints
Journal of Systems Architecture: the EUROMICRO Journal
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In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size share a common and unique cache slot. Instruction cache conflicts can be partially handled at linked time by procedure placement. Pettis and ...