Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The memory/logic interface in FPGA's with large embedded memory arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Power Modelling in Field Programmable Gate Arrays (FPGA)
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Exploring Optimal Cost-Performance Designs for Raw Microprocessors
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Generic Design Space Exploration for Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Journal of Embedded Computing - Cache exploitation in embedded systems
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Many academic works in computer engineering focus on reconfigurable architectures and associated tools. Fine-grain architectures, field programmable gate arrays (FPGAs), are the most well-known structures of reconfigurable hardware. Dedicated tools (generic or specific) allow for the exploration of their design space to choose the best architecture characteristics and/or to explore the application characteristics. The aim is to increase the synergy between the application and the architecture in order to get the best performance. However, there is no generic tool to perform such an exploration for coarse-grain or heterogeneous-grain architectures, just a small number of very specific tools are able to explore a limited set of architectures. To address this major lack, in this paper we propose a new design space exploration approach adapted to fine- and coarse-grain granularities. Our approach combines algorithmic and architecture explorations. It relies on an automatic estimation tool which computes the communication hierarchical distribution and the architectural processing resources use rate for the architecture under exploration. Such an approach forwards the rapid definition of efficient reconfigurable architectures dedicated to one or several applications.