Proceedings of the conference on Design, automation and test in Europe
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing
Journal of VLSI Signal Processing Systems
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Proceedings of the 31st annual international symposium on Computer architecture
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Proceedings of the 2006 international symposium on Low power electronics and design
A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms
Journal of VLSI Signal Processing Systems
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
The Chameleon architecture for streaming DSP applications
EURASIP Journal on Embedded Systems
DART: a functional-level reconfigurable architecture for high energy efficiency
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Dynamic context compression for low-power coarse-grained reconfigurable architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-area multi-link interconnect architecture for GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Control for power gating of wires
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power reconfiguration technique for coarse-grained reconfigurable architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Synchroscalar: initial lessons in power-aware design of a tile-based embedded architecture
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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In this paper, we present and analyze a number of interconnect architectures for reconfigurable systems targeting applications in the areas of wireless communication and multimedia processing. Several interconnect architectures suitable for heterogeneous elements are proposed and then a methodology to evaluate the architectures is described. The results indicate that the hierarchical generalized mesh structure shows the most promise in terms of energy efficiency, as it can optimize both local and global connections.