VLSI array processors
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Adaptive filter theory (3rd ed.)
Adaptive filter theory (3rd ed.)
Matrix computations (3rd ed.)
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Multiuser Detection
OFDM Wireless LANs: A Theoretical and Practical Guide
OFDM Wireless LANs: A Theoretical and Practical Guide
Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Ultra Low Power CORDIC Processor for Wireless Communication Algorithms
Journal of VLSI Signal Processing Systems
An efficient square-root algorithm for BLAST
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 02
Introduction to Space-Time Wireless Communications
Introduction to Space-Time Wireless Communications
Fast, rank adaptive subspace tracking and applications
IEEE Transactions on Signal Processing
Blind multiuser detection: a subspace approach
IEEE Transactions on Information Theory
Automated architecture synthesis for parallel programs on FPGA multiprocessor systems
Microprocessors & Microsystems
Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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We propose a configurable and scalable architecture targeted for the implementation of advanced wireless communication algorithms based on matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the representation of the algorithm in Matlab/Simulink. The Simulink description is parsed and the algorithm's Dependence Flow Graph is derived, which is scheduled and space---time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable VLIW DSP processors.