Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
Queue - Multiprocessors
Design space exploration and prototyping for on-chip multimedia applications
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms
Journal of VLSI Signal Processing Systems
Design of adaptive multiprocessor on chip systems
Proceedings of the 20th annual conference on Integrated circuits and systems design
Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology
EURASIP Journal on Embedded Systems
High-level modelling and exploration of coarse-grained re-configurable architectures
Proceedings of the conference on Design, automation and test in Europe
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
LPNMR '09 Proceedings of the 10th International Conference on Logic Programming and Nonmonotonic Reasoning
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a concept for automated architecture synthesis for adaptive multiprocessors on chip, in particular for Field-Programmable Gate-Array (FPGA) devices. Given a parallel program, the intent is to simultaneously allocate processor resources and the corresponding communication network, and at the same time, to map the parallel application to get an optimum application-specific architecture. This approach builds up on a previously proposed design platform that automates system integration and FPGA synthesis for such architectures. As a result, the overall concept offers an automated design approach from application mapping to system and FPGA configuration. The automated synthesis is based on combinatorial optimization. Automation is possible because a solvable Integer Linear Programming (ILP) model that captures all necessary design trade-off parameters of such systems has been found. Experimental results to study the feasibility of the automated synthesis indicate that problems with sizes that can be encountered in the embedded domain can be readily solved. Results obtained underscore the need for an automated synthesis for design space exploration.