A VHDL primer
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
RF microelectronics
Functional verification of large ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
HERCULES—a system for high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Low-power silicon architecture for wireless communications: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Rapid prototyping for wireless designs: the five-ones approach
Signal Processing - From signal processing theory to implementation
Chip-level channel equalization in WCDMA downlink
EURASIP Journal on Applied Signal Processing
EURASIP Journal on Applied Signal Processing
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prototype experience for MIMO BLAST over third-generation wireless system
IEEE Journal on Selected Areas in Communications
Automated architecture synthesis for parallel programs on FPGA multiprocessor systems
Microprocessors & Microsystems
Simulation and emulation of MIMO wireless baseband transceivers
EURASIP Journal on Wireless Communications and Networking - Special issue on simulators and experimental testbeds design and development for wireless networks
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hard-ware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.