Knowledge based control in micro-architecture design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Statistics for parallelism and abstraction level in digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Distributed process groups in the V Kernel
ACM Transactions on Computer Systems (TOCS)
MIS: A Multiple-Level Logic Optimization System
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The FSM network model for behavioral synthesis of control-dominated machines
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Relevant issues in high-level connectivity synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
ISIS: a system for performance driven resource sharing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
An Automaton Model for Scheduling Constraints in Synchronous Machines
IEEE Transactions on Computers
Interconnection synthesis with geometric constraints
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Parallel Distributed-Time Logic Simulation
IEEE Design & Test
System Specification with the SpecCharts Language
IEEE Design & Test
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Specification of timing constraints for controller synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology
EURASIP Journal on Embedded Systems
Optimal synthesis of control logic from behavioral specifications
Integration, the VLSI Journal
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This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation. We describe HERCULES, a system for high-level synthesis developed at Stanford University. In particular, we address the hardware description problem, behavioral synthesis and optimization using a method called the reference stack, and the mapping of behavior onto a structure. We present a model for control based on sequencing graphs that supports multiple threads of execution flow, allowing varying degree of parallelism in the resulting hardware. Results are then presented for three examples: MC6502, Intel8251 and FRISC, a 16-bit microprocessor.