Specification of timing constraints for controller synthesis

Authors:
Rumi Zahir;Wolfgang Fichtner
Affiliations:
Integrated Systems Laboratory, ETH Zürich, 8092 Zürich, Switzerland;Integrated Systems Laboratory, ETH Zürich, 8092 Zürich, Switzerland
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

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Abstract

For controller synthesis to be successful, detailed knowledge of the timing constraints of the system under synthesis is essential. This paper presents a method for extracting timing constraints from a behavioral description, architectural restrictions, component timing requirements and protocol specifications. The timing constraints are combined in a timing constraint graph that can be solved in polynomial time using algorithms known from symbolic layout compaction.