Scheduling under resource constraints and module assignment
Integration, the VLSI Journal
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Specification of timing constraints for controller synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Scheduling a minimum dependence in FSMs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid estimation of control delay from high-level specifications
Proceedings of the 43rd annual Design Automation Conference
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
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