Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Towards a high-level power estimation capability
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Timing analysis in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power management techniques for control-flow intensive designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
A power modeling and characterization method for macrocells using structure information
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Proceedings of the 6th international workshop on Hardware/software codesign
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Estimation of power sensitivity in sequential circuits with power macromodeling application
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Energy-per-cycle estimation at RTL
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Regression-based RTL power models for controllers
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
Architecture-level power estimation and design experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Frequency-domain supply current macro-model
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Parameterized RTL power models for soft macros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
High-level current macro-model for power-grid analysis
Proceedings of the 39th annual Design Automation Conference
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Probabilistic Bottom-Up RTL Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
A path based modeling approach for dynamic power estimation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on word-level data, we construct piecewise linear models that capture the variation of output glitching activity and power consumption with various word-level parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, registers, vector logic operators, etc. Since the final implementation of the controller is not available during high-level design iterations, we develop techniques that estimate glitching activity at control signals using control expressions and partial delay information. Experiments on example RTL designs resulted in power estimates that were within 7% of those produced by an inhouse power analysis tool on the final gate-level implementation.