PowerPC 603 microprocessor power management
Communications of the ACM
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Clock period optimization during resource sharing and assignment
DAC '94 Proceedings of the 31st annual Design Automation Conference
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Glitch analysis and reduction in register transfer level power optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An effective power management scheme for RTL design based on multiple clocks
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Controller re-specification to minimize switching activity in controller/data path circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Transforming control-flow intensive designs to facilitate power management
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
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This paper presents a low-overhead controller-based powermanagement technique that re-specifies control signals to reconfigureexisting multiplexer networks and functional units to minimizeunnecessary activity. We demonstrate that conventional powermanagement techniques may often not be suited to control-flowintensive designs, and provide a comprehensive analysis of thepotential negative effects of power management on circuit delay,glitching activity at control and data path signals, and formationof false combinational cycles. We present techniques to performpower management through controller re-specification while avoidingthe above negative effects, and demonstrate the efficiency ofthe techniques through experiments.