Glitch analysis and reduction in register transfer level power optimization

  • Authors:
  • Anand Raghunathan;Sujit Dey;Niraj K. Jha

  • Affiliations:
  • Department of EE, Princeton University, Princeton, NJ;C&C Research Labs, NEC, Inc., Princeton, NJ;Department of EE, Princeton University, Princeton, NJ

  • Venue:
  • DAC '96 Proceedings of the 33rd annual Design Automation Conference
  • Year:
  • 1996

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Abstract