Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Node sampling: a robust RTL power modeling approach
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On-chip transient current monitor for testing of low-voltage CMOS IC
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Energy-per-cycle estimation at RTL
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Frequency-domain supply current macro-model
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Transient Power Supply Voltage (VDDT) Analysis for Detecting IC Defects
Proceedings of the IEEE International Test Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
Dynamic Power Supply Current Testing of SRAMs
ATS '98 Proceedings of the 7th Asian Test Symposium
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Improved CMOS BICS for On-Line Testing
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics
Proceedings of the conference on Design, automation and test in Europe
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Defect Detection using Power Supply Transient Signal Analysis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Transient Current Testing of 0.25 µm CMOS Devices
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical threshold formulation for dynamic Idd test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor
Journal of Electronic Testing: Theory and Applications
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We evaluate the possibilities of transient current testing practical implementation by comparing the transient supply current signature at the IC supply pins to its internal behavior. This analysis is key to correlate the internal circuit block transient current shape to the waveform measured outside the IC. These waveforms may differ significantly due to the power supply grid, whose capacitive and inductive components can modify both the frequency and magnitude components of the transient current. Given the complexity of today ICs, an accurate description of the circuit power grid is required to investigate the merits of transient current testing (idd(t)) approaches. In this work we develop and analyze a hierarchical power-grid equivalent circuit to evaluate the supply current frequency components and their distribution over the power/ground grid hierarchy. This is a key step to determine the feasibility of on-chip vs. off-chip idd(t) strategies and their posterior application to on-line testing.