A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Full-chip verification of UDSM designs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Node sampling: a robust RTL power modeling approach
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Estimation of power sensitivity in sequential circuits with power macromodeling application
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Energy-per-cycle estimation at RTL
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Analytical macromodeling for high-level power estimation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Speeding up power estimation of embedded software
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Regression-based RTL power modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A static power estimation methodolodgy for IP-based design
Proceedings of the conference on Design, automation and test in Europe
Characterization-free behavioral power modeling
Proceedings of the conference on Design, automation and test in Europe
A new method for constructing IP level power model based on power sensitivity
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Frequency-domain supply current macro-model
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Parameterized RTL power models for soft macros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Memory power models for multilevel power estimation and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level current macro-model for power-grid analysis
Proceedings of the 39th annual Design Automation Conference
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Ramp Up/Down Functional Unit to Reduce Step Power
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Power Models for Semi-autonomous RTL Macros
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Probabilistic Power Estimation for Digital Signal Processing Architectures
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
A Markov chain sequence generator for power macromodeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Instruction Prediction for Step Power Reduction
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Power Macromodeling for a High Quality RT-Level Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
HyPE: hybrid power estimation for IP-based programmable systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
A path based modeling approach for dynamic power estimation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A multi-model power estimation engine for accuracy optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A design automation and power estimation flow for RFID systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power estimation technique for DSP architectures
Digital Signal Processing
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Dynamic power estimation for deep submicron circuits with process variation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design of complex image processing systems in ESL
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Automatic memory partitioning and scheduling for throughput and power optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A precise high-level power consumption model for embedded systems software
EURASIP Journal on Embedded Systems
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis
Proceedings of the International Conference on Computer-Aided Design
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A modeling approach is presentedthat captures the dependence of the power dissipationof a combinational logic circuit on its input/outputsignal switching activity.The resultingpower macromodel, consisting of a single three dimensionaltable, can be used to estimate the powerconsumed in the circuit for any given input/outputsignal statistics.Given a low-level (typically gate-level)description of the circuit, we describe a characterizationprocess by which such a table modelcan be automatically built.In contrast to otherproposed techniques, this can be done for any givenlogic circuit without any user intervention, and appliesto all possible input/output signal statistics;it does not require one to construct specialized analyticalequations for the power dissipation.Thethree dimensions of our table-based model are theaverage input signal probability, average input transitiondensity, and average output zero-delay transition density.This approach has been implemented and modelshave been built for many benchmark circuits.Overa wide range of input signal statistics, we show thatthis model gives very good accuracy, with an RMSerror of under about 6%.