Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automatic characterization and modeling of power consumption in static RAMs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Clustered Table-Based Macromodels for RTL Power Estimation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Instantaneous current modeling in a complex VLIW processor core
ACM Transactions on Embedded Computing Systems (TECS)
HyPE: hybrid power estimation for IP-based programmable systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Several approaches that address early power estimation in digital design have been published in the last years. Most of them are based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist. In this paper we present a summary of RTPow, a proprietary tool dealing with the RT-level power estimation, relying on a top-down estimation engine that does not perform any type of on-the-fly logic synthesis when analyzing the HDL description. In addition, a set of power macromodeling capabilities have been developed as well, to enable an effective power budgeting and automatic bottom-up power characterization methodology.