ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Clustered Table-Based Macromodels for RTL Power Estimation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Power Macromodeling for a High Quality RT-Level Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Today's design community need tools that address early power estimation, making it possible to find the optimal design trade-offs without respinning to explore the whole chip. Several approaches based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist and then create suitable power models have been published in the last years. In this paper we present some applications of RTPow, a proprietary tool dealing with the RT-level power estimation. The innovative estimation engine that does not perform any type of on-the-fly logic synthesis, but analyze the HDL description from the functionality point of view, permits a drastic time saving. Besides this top-down estimation, RTPow is able to perform a series of power macromodels and the bottom-up approach that enable an effective power budgeting. The first is an Adaptive Gaussian Noise Filter (28K Eq.Gate), described in VHDL, the second is a Motion Estimation and Compensation Device for Video Field Rate Doubling Application (171K Eq.Gate) also described in VHDL. The third is a micro-processor core (111K Eq.Gate) described using Verilog language.