Power macro-models for DSP blocks with application to high-level synthesis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy-per-cycle estimation at RTL
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Analytical macromodeling for high-level power estimation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A static power estimation methodolodgy for IP-based design
Proceedings of the conference on Design, automation and test in Europe
Power Models for Semi-autonomous RTL Macros
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A Markov chain sequence generator for power macromodeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power Macromodeling for a High Quality RT-Level Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
HyPE: hybrid power estimation for IP-based programmable systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Power estimation technique for DSP architectures
Digital Signal Processing
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In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel, consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such a equation-based model can be automatically built. The four variables of our model are the average input signal probability, average input switching activity, average input spatial correlation coefficient and average output zero-delay switching activity. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits.