The probability of error detection in sequential circuits using random test vectors
Journal of Electronic Testing: Theory and Applications
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power modeling for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A static power estimation methodolodgy for IP-based design
Proceedings of the conference on Design, automation and test in Europe
Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
A Monte Carlo approach for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic simulation for reliability analysis of CMOS VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HyPE: hybrid power estimation for IP-based systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate power dissipation of the system just by using the statistics of the macro-block's primary inputs. In experiments with the DSP system, the average error is 26%.