Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Analytical macromodeling for high-level power estimation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A Markov chain sequence generator for power macromodeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Lookup Table Power Macro-Models for Behavioral Library Components
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
An overview of a compiler for mapping software binaries to hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Power estimation of embedded multiplier blocks in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of dividers implemented in FPGAs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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As more and more complex applications are implemented on FPGAs, high-level design tools are needed to reduce the design time. A good high-level synthesis tool usually has an automated design space exploration pass to determine the effects of various compiler optimizations on the area and power of the synthesized hardware. Such a pass needs early estimation of area and power. Towards this end, we have developed high-level equation based area and power macro-models for various RTL level operators such as adders, multipliers, and logical operators. The area model is parameterized with the bit width of the device and the power model takes into account input switching activity and input spatial correlation as well as input bit width. These models are derived by actual synthesis of these RTL operators using back-end logic synthesis and place-and-route tools. Compared with the other approaches, our method generated a uniform macro-model for each operator with fewer coefficients and sometimes lower degrees. It is also easier to analyze the power sensitivity to different parameters. Experimental results show that these area and power models are accurate and efficient.