Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Low power and high speed multiplication design through mixed number representations
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
54x54-bit radix-4 multiplier based on modified booth algorithm
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A routing fabric for monolithically stacked 3D-FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Floorplan-based FPGA interconnect power estimation in DSP circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Power estimation of dividers implemented in FPGAs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
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The use of embedded multiplier blocks has become a norm in DSP applications due to their high performance and low power consomption. However, as their implementation details in commercial field-programmable gate arrays are not available to users, and the power estimates given by the tested low-level tool are not accurate enough to validate high-level models, the work on power estimation of these blocks is very limited. We present a dynamic power estimation methodology for the embedded multipliers in Xilinx Virtex-II Pro chips. The methodology is an adaptation of an existing power estimation method for lookup-table-based components and uses information about the type of architecture of the embedded block. The power model is characterized and verified by on-board measurements and is ready for integration with high-level power optimization techniques. The experimental results show that the average accuracy of the model is higher than the average accuracy of the low-level commercial tool.