Integer Multiplication with Overflow Detection or Saturation
IEEE Transactions on Computers - Special issue on computer arithmetic
Sign bit reduction encoding for low power applications
Proceedings of the 42nd annual Design Automation Conference
Sign Bit Reduction Encoding For Low Power Applications
Journal of Signal Processing Systems
Partitioning and gating technique for low-power multiplication in video processing applications
Microelectronics Journal
Power estimation of embedded multiplier blocks in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder. The high speed operation is achieved through the Carry-Propagation-Free (CPF) accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average.