Partitioning and gating technique for low-power multiplication in video processing applications

Authors:
Hau T. Ngo;Vijayan K. Asari
Affiliations:
Department of Electrical and Computer Engineering, United States Naval Academy, Annapolis, MD 21402, USA;Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529, USA
Venue:
Microelectronics Journal
Year:
2009

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Abstract

In this paper, we propose a partitioning and gating technique for the design of a high performance and low-power multiplier for kernel-based operations such as 2D convolution in video processing applications. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching. Input pixels in the video stream are partitioned into halves to increase the possibility of detecting special values. It is observed that the proposed scheme helps to reduce dynamic power consumption in the 2D convolution operations up to 33%.