A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reconfigurable Low Energy Multiplier for Multimedia System Design
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Partitioning and gating technique for low-power multiplication in video processing applications
Microelectronics Journal
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Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and computer architectures. Although Boolean multipliers have natural power awareness to the changing of input precision, deeply pipelined designs do not have this benefit. A 2-dimensional pipeline gating scheme is proposed in this paper to solve this problem and improve the power awareness in these designs. 2-Dimensional pipeline gating is to gate the clock to registers in both vertical direction (data flow direction in pipeline) and horizontal direction (within each pipeline stage). This technique only needs very little additional area and the overhead is hardly noticeable. A set of array multipliers were designed and tested. Results show that the new 16-bit array multiplier using this technique has an average power saving of 66% and an average latency reduction of 47% over original design under equal input precision probabilities.