Input space adaptive design: a high-level methodology for energy and performance optimization
Proceedings of the 38th annual Design Automation Conference
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications
Journal of VLSI Signal Processing Systems
Integration, the VLSI Journal - Special issue: Low-power design techniques
Integration, the VLSI Journal
On the design of reconfigurable multipliers for integer and Galois field multiplication
Microprocessors & Microsystems
Integration, the VLSI Journal - Special issue: Low-power design techniques
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This paper proposes a reconfigurable-pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier, disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low save energy. To evaluate the efficiency of our multiplier architecture, we have designed a multiplier-based inverse quantizer (IQ) for MPEG-2 MP@ML. Pipelines are dynamically reconfigured according to the size of the picture and the number of nonzero quantized DCT coefficients per block. In comparison with corresponding multiplier implementations that use conventional pipelines, our reconfigurable multipliers dissipate about 31-58% less energy. Relative energy savings increase with decreasing data rates, since our reconfigurable structures stay in a low energy configuration for proportionately longer time.