The Art of Computer Programming Volumes 1-3 Boxed Set
The Art of Computer Programming Volumes 1-3 Boxed Set
The Design of Rijndael
IEEE Transactions on Computers
Optimal Finite Field Multipliers for FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A hybrid ASIC and FPGA architecture
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reconfigurable Low Energy Multiplier for Multimedia System Design
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Error Control Coding: From Theory to Practice
Error Control Coding: From Theory to Practice
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2^m)
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
An iterative logarithmic multiplier
Microprocessors & Microsystems
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions.