Coarse grain reconfigurable architecture (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
A Compilation Framework for a Dynamically Reconfigurable Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems
The Journal of Supercomputing
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Signal Processing in Wireless Terminals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
Reconfigurable signal processing and hardware architecture for broadband wireless communications
EURASIP Journal on Wireless Communications and Networking
Mapping wireless communication algorithms onto a reconfigurable architecture
The Journal of Supercomputing
A Reconfigurable Architecture for Wireless Communication Systems
ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology
EURASIP Journal on Embedded Systems
An energy-efficient reconfigurable baseband processor for wireless communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design flow instantiation for run-time reconfigurable systems: a case study
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speedups and energy reductions from mapping DSP applications on an embedded reconfigurable system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the design of reconfigurable multipliers for integer and Galois field multiplication
Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Pipeline FFT architectures optimized for FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
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The Fourth Generation (4G) network is expected to serve mobile subscribers under dynamic network conditions and offer any type service: anytime, anywhere, and anyhow. Two such technologies that can respond to the above said services are Wideband Code Division Multiple Access (WCDMA) and Orthogonal Frequency Division Multiplexing (OFDM). The main contribution of this paper is to propose a dedicated hardware module which can reconfigure itself either to the OFDM Wireless LAN or WCDMA standard. In this paper, Fast Fourier Transform(FFT) algorithm is implemented for OFDM standard, and rake receiver is implemented for WCDMA standard. Initially efficient implementations of these two algorithms are tested separately and identified the resources utilized by them. Then the new hardware architecture, which configures to any one of these two standards on demand, is proposed. This architecture efficiently shares the resources needed for these two standards. The proposed architecture is simulated using ModelSimSE v6.5 and mapped onto a virtex 5 FPGA device (xc5v1x30ff324) using the tool Xilinx ISE 9.2i, and the results are compared with the standard approach. These results show that the proposed hardware architecture utilizes less number of resources compared to the conventional Reconfigurable Receiver Architecture System.