A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication

  • Authors:
  • Jürgen Becker;Manfred Glesner

  • Affiliations:
  • Darmstadt University of Technology, Institute of Microelectronic Systems, Karlstr. 15, D-64283 Darmstadt, Germany Fax: ++49 6151 16 4936becker@mes.tu-darmstadt.de;Darmstadt University of Technology, Institute of Microelectronic Systems, Karlstr. 15, D-64283 Darmstadt, Germany Fax: ++49 6151 16 4936glesner@mes.tu-darmstadt.de

  • Venue:
  • The Journal of Supercomputing
  • Year:
  • 2001

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Abstract

The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for future mobile communication applications. Based thereupon, the architecture design of flexible system-on-chip solutions in the digital baseband processing for future mobile radio devices is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.