Pipeline architectures for morphologic image analysis
Machine Vision and Applications
Automatic generation of morphological set recognition algorithms
Automatic generation of morphological set recognition algorithms
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Computer and Robot Vision
Digital Picture Processing
Active pages: a computation model for intelligent memory
Proceedings of the 25th annual international symposium on Computer architecture
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis and FPGA Implementation of Image Restoration under Resource Constraints
IEEE Transactions on Computers
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Parallel Image Matching on PC Cluster
Proceedings of the 8th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
A reconfigurable architecture for autonomous visual-navigation
Machine Vision and Applications
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
WILDFIRE(tm) Heterogeneous Adaptive Parallel Processing Systems
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
The use of configurable computing for computational kernels in scientific simulations
Future Generation Computer Systems
FPGA-based configurable systolic architecture for window-based image processing
EURASIP Journal on Applied Signal Processing
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
The use of configurable computing for computational kernels in scientific simulations
Future Generation Computer Systems
High-performance automatic target recognition through data-specific VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
Interconnect estimation for mesh-based reconfigurable computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
| Hi-index | 4.10 |
Hardware designers typically must perform extensive behavioral testing of a new concept before proceeding with an implementation. Due to the enormous processing time required to simulate a complex image-processing system executing a VHDL model with a representative data set even on a fast workstation is not practical. Days even weeks, are commonly needed to simulate the processing of a full-sized image. And since some applications process sequences of images, designers may need several hundred image simulations to adequately analyze only a few seconds of data. Because of this, they may be forced into a trade-off between how much testing can be afforded versus an acceptable risk in allowing a silicon iteration. The authors discuss an alternative, automated approach: transforming the structural representation (or transforming a behavioral model) into a real-time implementation. With their VTSplash custom computing platform, a designer can proceed from a behavioral description of the image-processing task to a functioning prototype that can perform the task at full speed (rapid prototyping). Reconfiguration from one image-processing task to another takes just seconds. The authors explore the utility of custom computing machinery for accelerating the development, testing, and prototyping of a diverse set of image-processing applications. They describe several implemented image-processing tasks and conclude with task performance evaluation.