Introduction to nMOS & VLSI systems design
Introduction to nMOS & VLSI systems design
Data compression using dynamic Markov modelling
The Computer Journal
Suffix arrays: a new method for on-line string searches
SIAM Journal on Computing
Fast algorithms for sorting and searching strings
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Perspectives of Reconfigurable Computing in Research, Industry and Education
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Modifications of the Burrows and Wheeler Data Compression Algorithm
DCC '99 Proceedings of the Conference on Data Compression
Implementing the Context Tree Weighting Method for Text Compression
DCC '00 Proceedings of the Conference on Data Compression
Move-to-Front and Inversion Coding
DCC '00 Proceedings of the Conference on Data Compression
On the Performance of BWT Sorting Algorithms
DCC '00 Proceedings of the Conference on Data Compression
Rapid identification of repeated patterns in strings, trees and arrays
STOC '72 Proceedings of the fourth annual ACM symposium on Theory of computing
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
IBM Journal of Research and Development
Efficient Algorithms for the Inverse Sort Transform
IEEE Transactions on Computers
Computing the inverse sort transform in linear time
ACM Transactions on Algorithms (TALG)
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Abstract: Due to high bandwidth requirements up to 2 Mbits/sec in third generation mobile communication systems, efficient data compression approaches are necessary to reduce communication and storage costs. Recent VLSI technologies status promises complete System-on-Chip (SoC) solutions for both mobile and network based communication systems, including new compression algorithms based on Burrows-Wheeler transform (BWT). The most complex task of the BWT algorithm is its lexicographic sorting of n cyclic rotations of a given string of n characters. The paper discusses the feasibility and VLSI implementation of this scalable BWT architecture in simulating and prototyping its systolic highly utilized hardware structure with Virtex FPGAs.