Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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In this paper we present performance models of communication structures in hardware/software systems as the basis for communication architecture synthesis with real-time constraints. Based on a partitioned mixed hardware/ software description and communication constraints a thorough analysis of different communication structures is carried out to determine the optimal communication architecture. The hardware/software system will be emulated as an architecture-precise prototype on a real-time platform