Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
DSP system integration and prototyping with FPGAs
Journal of VLSI Signal Processing Systems - Special issue on field-programmable gate arrays
The image processing handbook (3rd ed.)
The image processing handbook (3rd ed.)
Procedural texture mapping on FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Implementing a RAKE receiver for wireless communications on an FPGA-based computer system
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Digital Image Restoration
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Collaborative and reconfigurable object tracking
The Journal of Supercomputing
Reconfiguration in network of embedded systems: Challenges and adaptive tracking case study
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
| Hi-index | 14.98 |
Programmable logic is emerging as an attractive solution for many digital signal processing applications. In this work, we have investigated issues arising due to the resource constraints of FPGA-based systems. Using an iterative image restoration algorithm as an example we have shown how to manipulate the original algorithm to suit it to an FPGA implementation. Consequences of such manipulations have been estimated, such as loss of quality in the output image. We also present performance results from an actual implementation on a Xilinx FPGA. Our experiments demonstrate that, for different criteria, such as result quality or speed, the best implementation is different as well.