Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Experiments with a Program Timing Tool Based on Source-Level Timing Schema
Computer - Special issue on real-time systems
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
An adaptive machine architecture and compiler for dynamic processor reconfigurations
An adaptive machine architecture and compiler for dynamic processor reconfigurations
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
A tool for processor instruction set design
EURO-DAC '94 Proceedings of the conference on European design automation
Developing a reflective model of collaborative systems
ACM Transactions on Computer-Human Interaction (TOCHI)
HGA: a hardware-based genetic algorithm
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Clustering for improved system-level functional partitioning
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Profiling in the ASP codesign environment
ISSS '95 Proceedings of the 8th international symposium on System synthesis
DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
The design of mixed hardware/software systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Computer Vision Algorithms on Reconfigurable Logic Arrays
IEEE Transactions on Parallel and Distributed Systems
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Automatic detection of recurring operation patterns
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Dynamically reconfigurable architecture for image processor applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware/software co-design of a fuzzy RISC processor
Proceedings of the conference on Design, automation and test in Europe
A software development tool chain for a reconfigurable processor
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
IEEE Transactions on Parallel and Distributed Systems
Hardware-software cosynthesis for microcontrollers
Readings in hardware/software co-design
A pipelined configurable gate array for embedded processors
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
The Garp Architecture and C Compiler
Computer
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Compiler Optimizations for Adaptive EPIC Processors
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Task-Parallel Programming of Reconfigurable Systems
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
The MOLEN rho-mu-Coded Processor
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Compilation for FPGA-Based Reconfigurable Hardware
IEEE Design & Test
Hardware/software partitioning of software binaries
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the tenth international symposium on Hardware/software codesign
Towards a Model for Hardware and Software Functional Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Software acceleration using programmable logic: is it worth the effort?
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Macro-instruction generation for dynamic logic caching
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
VaWiRAM: a variable width random access memory module
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Architecture of a FPGA-based coprocessor: the PAR-1
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Bandwidth Management with a Reconfigurable Data Cache
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Exploring the design space of LUT-based transparent accelerators
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Extracting and improving microarchitecture performance on reconfigurable architectures
International Journal of Parallel Programming - Special issue: The next generation software program
Microprocessors & Microsystems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Architecture and Development Flow of the S5 Software Configurable Processor
Journal of VLSI Signal Processing Systems
Improving instruction level parallelism through reconfigurable units in superscalar processors
ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
Finding optimal hardware/software partitions
Formal Methods in System Design
Achieving programming model abstractions for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Embedded Computing Systems (TECS)
The Instruction-Set Extension Problem: A Survey
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Computers and Electrical Engineering
Proceedings of the 6th ACM conference on Computing frontiers
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
HiPC'08 Proceedings of the 15th international conference on High performance computing
Zero logic overhead integration of partially reconfigurable modules
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Hardware parallelism vs. software parallelism
HotPar'09 Proceedings of the First USENIX conference on Hot topics in parallelism
Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design, implementation, and verification of an adaptable processor in lava HDL
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
High-performance automatic target recognition through data-specific VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Processor design using a functional hardware description language
Microprocessors & Microsystems
| Hi-index | 4.11 |
The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented.