Processor Acceleration Through Automated Instruction Set Customization

  • Authors:

  • Nathan Clark;Hongtao Zhong;Scott Mahlke

  • Affiliations:

  • Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor,MI;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor,MI;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor,MI

  • Venue:
  • Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2003

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Abstract

Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meetthe growing performance and power demands of embeddedapplications. Hardware, in the form of new function units(or co-processors), and the corresponding instructions, areadded to a baseline processor to meet the critical computational demands of a target application. The central challenge with this approach is the large degree of human effortrequired to identify and create the custom hardware units,as well as porting the application to the extended processor.In this paper, we present the design of a system to automate the instruction set customization process. A dataflowgraph design space exploration engine efficiently identifiesprofitable computation subgraphs from which to create custom hardware, without artificially constraining their sizeor shape. The system also contains a compiler subgraphmatching framework that identifies opportunities to exploitand generalize the hardware to support more computationgraphs. We demonstrate the effectiveness of this systemacross a range of application domains and study the applicability of the custom hardware across the domain.