Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
A graph covering algorithm for a coarse grain reconfigurable system
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic selection of application-specific reconfigurable processor extensions
Proceedings of the conference on Design, automation and test in Europe
An efficient algorithm for custom instruction enumeration
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ASAM: Automatic architecture synthesis and application mapping
Microprocessors & Microsystems
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This paper presents a new constraint-driven method for fast identification of computational patterns that is a part of DURASE system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The patterns identified by our system form a base for application specific instruction selection and processor extension generation. Our method identifies all computational patterns directly from an application graph satisfying all architectural and technological constraints imposed by target processors and FPGA devices. The considered constraints include a number of inputs and outputs, a number of operators, and a delay of the pattern critical path. Therefore the identified patterns can be well tailored to target processors. Our approach uses heavily constraint programming methods, which makes it possible to mix graph isomorphism constraints with other constraints in one formal environment. We have extensively evaluated our algorithm on MediaBench and MiBench benchmarks with tough architectural and technological constraints. The obtained patterns have good coverage of application graphs while limiting number of operators and fulfill architectural and technological constraints.