A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
A DAG-based design approach for reconfigurable VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Introduction of local memory elements in instruction set extensions
Proceedings of the 41st annual Design Automation Conference
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Scalable subgraph mapping for acyclic computation accelerators
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Supporting multiple-input, multiple-output custom functions in configurable processors
Journal of Systems Architecture: the EUROMICRO Journal
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
Proceedings of the International Symposium on Code Generation and Optimization
Optimizing instruction-set extensible processors under data bandwidth constraints
Proceedings of the conference on Design, automation and test in Europe
Polynomial-time subgraph enumeration for automated instruction set extension
Proceedings of the conference on Design, automation and test in Europe
Increasing data-bandwidth to instruction-set extensions through register clustering
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Automatic selection of application-specific reconfigurable processor extensions
Proceedings of the conference on Design, automation and test in Europe
Constraint-Driven Identification of Application Specific Instructions in the DURASE System
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Algorithms for the automatic extension of an instruction-set
Proceedings of the Conference on Design, Automation and Test in Europe
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
M2E: a multiple-input, multiple-output function extension for RISC-Based extensible processors
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Resource-constrained high-level datapath optimization in ASIP design
Proceedings of the Conference on Design, Automation and Test in Europe
Complexity of computing convex subgraphs in custom instruction synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.