Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
From ASIC to ASIP: The Next Design Discontinuity
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Synthesis-driven Exploration of Pipelined Embedded Processors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient ASIP design for configurable processors with fine-grained resource sharing
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Design-space exploration of resource-sharing solutions for custom instruction set extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient design space exploration for component-based system design
Proceedings of the International Conference on Computer-Aided Design
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In this work, we study the problem of optimizing the datapath under resource constraint in the high-level synthesis of Application-Specific Instruction Processor (ASIP). We propose a two-level dynamic programming (DP) based heuristic algorithm. At the inner level of the proposed algorithm, the instructions are sorted in topological order, and then a DP algorithm is applied to optimize the topological order of the datapath. At the outer level, the space of the topological order of each instruction is explored to iteratively improve the solution. Compared with an optimal brutal-force algorithm, the proposed algorithm achieves near-optimal solution, with only 3% more performance overhead on average but significant reduction in runtime. Compared with a greedy algorithm which replaces the DP inner level with a greedy heuristic approach, the proposed algorithm achieves 48% reduction in performance overhead.