From ASIC to ASIP: The Next Design Discontinuity

Authors:
Affiliations:
Venue:
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Year:
2002

Citing 0
Cited 27

A Scalable Application-Specific Processor Synthesis Methodology

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Instruction set extension with shadow registers for configurable processors

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Microcoded coprocessor for embedded secure biometric authentication systems

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Architecture and compiler optimizations for data bandwidth improvement in configurable processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing custom registers in application-specific instruction set processors for register spills elimination

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology

Proceedings of the 17th ACM Great Lakes symposium on VLSI
RISPP: rotating instruction set processing platform

Proceedings of the 44th annual Design Automation Conference
Synthesis of object-oriented descriptions modeled at functional-level

ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model

Microprocessors & Microsystems
Embedded DSP Processor Design: Application Specific Instruction Set Processors

Embedded DSP Processor Design: Application Specific Instruction Set Processors
Efficient resource utilization for an extensible processor through dynamic instruction set adaptation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable synthesis methodology for application-specific processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers

Journal of Signal Processing Systems
A flexible hybrid simulation platform targeting multiple configurable processors SoC

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
The Instruction-Set Extension Problem: A Survey

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme

ACM Transactions on Design Automation of Electronic Systems (TODAES)
The ODYSSEY tool-set for system-level synthesis of object-oriented models

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Software pipelining support for transport triggered architecture processors

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Boosting single thread performance in mobile processors via reconfigurable acceleration

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Compiling for automatically generated instruction set extensions

Proceedings of the Tenth International Symposium on Code Generation and Optimization
A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of a low-power embedded processor architecture using asynchronous function units

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A 100 GOPS ASP based baseband processor for wireless communication

Proceedings of the Conference on Design, Automation and Test in Europe
Resource-constrained high-level datapath optimization in ASIP design

Proceedings of the Conference on Design, Automation and Test in Europe
Ingredients of adaptability: a survey of reconfigurable processors

VLSI Design
MORP: makespan optimization for processors with an embedded reconfigurable fabric

Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a significant move towards the use of programmable solutions of various forms 驴 increasingly referred to as programmable platforms. For the platform manufacturer, programmability provides higher volume to amortize design and manufacturing costs, as the same platform can be used over multiple related applications, as well as over generations of an application. For the application implementer, programmability provides a lower risk and shorter time-to-market implementation path. The flexibility provided by programmability comes with a performance and power overhead. This can be significantly mitigated by using application specific platforms, also referred to as Application Specific Instruction Set Processors (ASIPs). This paper details the reasons for this significant change in application implementation philosophy, provides illustrative contemporary evidence of this change, examines the space of application specific platforms, outlines fundamental problems in their development, and finally presents a methodology to deal with this changing design style.