Inheritance concept for signals in object-oriented extensions to VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Design and specification of embedded systems in Java using successive, formal refinement
DAC '98 Proceedings of the 35th annual Design Automation Conference
A framework for object oriented hardware specification, verification, and synthesis
Proceedings of the 38th annual Design Automation Conference
SUAVE: Painless Extension For An Object-Oriented VHDL
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
From ASIC to ASIP: The Next Design Discontinuity
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An assertion-based verification methodology for system-level design
Computers and Electrical Engineering
Journal of Computer and System Sciences
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We describe implementation of design automation tools that we have developed to automate system-level design using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of the embedded system and ASIP-based implementation of it. Two flows are automated: one synthesizes an ASIP from a given C++ class library, and the other one compiles a given C++ application to run on the ASIP that corresponds to the class library used in the application. This corresponds, respectively, to hardware- and software-generation for the embedded system while hardware-software interface is also automatically synthesized. This implementation also demonstrates three other advantages: firstly, the tool is capable of synthesizing polymorphism that, to the best of our knowledge, is unique among other C++ synthesizers; secondly, the tools generate an executable co-simulation model for the ASIP hardware and its software, and hence, enable early validation of the hardware-software system before full elaboration; and finally, error-prone language transformations are avoided by choosing C++ for application modeling and SystemC for ASIP implementation.