Object-oriented cosynthesis of distributed embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A framework for object oriented hardware specification, verification, and synthesis
Proceedings of the 38th annual Design Automation Conference
Software and hardware techniques for efficient polymorphic calls
Software and hardware techniques for efficient polymorphic calls
Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models
Proceedings of the conference on Design, automation and test in Europe - Volume 2
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
The ODYSSEY tool-set for system-level synthesis of object-oriented models
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Hi-index | 0.00 |
The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in OO co-designed embedded systems where resources are limited and where some functionality needs to be implemented in hardware to meet performance goals of the system. Our experimental results on real world embedded applications show up to 32.15% lower area and up to 5.1% higher speed compared to traditional implementation using VMT.