Data type analysis for hardware synthesis from object-oriented models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Object-oriented reuse methodology for VHDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Object-oriented modelling of parallel hardware systems
Proceedings of the conference on Design, automation and test in Europe
A flexible message passing mechanism for objective VHDL
Proceedings of the conference on Design, automation and test in Europe
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The ODYSSEY tool-set for system-level synthesis of object-oriented models
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mechanism. In addition to supporting object-orientation, these extended mechanisms improve the expressiveness of VHDL across the modeling spectrum, from high-level to gate-level. By choosing an incremental and evolutionary approach to extensions, SUAVE avoids major additions to the language that would complicate choice of mechanisms for expressing a design. The paper outlines the SUAVE extensions and illustrates their use through some examples. The mechanisms and examples are readily understood as incremental extensions to current modeling practices, hence "painless extension".