Statecharts: A visual formalism for complex systems
Science of Computer Programming
Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Java as a specification language for hardware-software systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Semantics and verification of action diagrams with linear timing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and specification of embedded systems in Java using successive, formal refinement
DAC '98 Proceedings of the 35th annual Design Automation Conference
Exploring the semantics of UML type structures with Z
FMOODS '97 Proceedings of the IFIP TC6 WG6.1 international workshop on Formal methods for open object-based distributed systems
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
The Unified Modeling Language user guide
The Unified Modeling Language user guide
The object constraint language: precise modeling with UML
The object constraint language: precise modeling with UML
The Unified Modeling Language reference manual
The Unified Modeling Language reference manual
Description and simulation of hardware/software systems with Java
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Inference of message sequence charts
Proceedings of the 22nd international conference on Software engineering
Proof, language, and interaction
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
A flexible message passing mechanism for objective VHDL
Proceedings of the conference on Design, automation and test in Europe
Reuse and protection of intellectual property in the SpecC system
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Esterel methodology for complex system design
Proceedings of MIGAS fourth session on Microelectronics for telecommunications : managing high complexity and mobility: managing high complexity and mobility
A framework for object oriented hardware specification, verification, and synthesis
Proceedings of the 38th annual Design Automation Conference
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Computer Networks
The formal execution semantics of SpecC
Proceedings of the 15th international symposium on System Synthesis
Timing Diagrams: Formalization and Algorithmic Verification
Journal of Logic, Language and Information
Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment
Formal Methods in System Design
A Formal Object-Oriented Analysis for Software Reliability: Design for Verification
FASE '01 Proceedings of the 4th International Conference on Fundamental Approaches to Software Engineering
What is in a Step: On the Semantics of Statecharts
TACS '91 Proceedings of the International Conference on Theoretical Aspects of Computer Software
Visual Specifications for Modular Reasoning about Asynchronous Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Smart Play-out of Behavioral Requirements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
An Automata Based Interpretation of Live Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Compositional Message Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Deciding Properties for Message Sequence Charts
FoSSaCS '98 Proceedings of the First International Conference on Foundations of Software Science and Computation Structure
On Formalizing the UML Object Constraint Language OCL
ER '98 Proceedings of the 17th International Conference on Conceptual Modeling
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
RuleBase: Model Checking at IBM
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
OCL: Syntax, Semantics, and Tools
Object Modeling with the OCL, The Rationale behind the Object Constraint Language
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
ASE '00 Proceedings of the 15th IEEE international conference on Automated software engineering
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Using Live Sequence Charts for Hardware Protocol Specification and Compliance Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
HW/SW Cosynthesis Using Statecharts and Symbolic Timing Diagrams
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
The e Language: A Fresh Separation of Concerns
TOOLS '01 Proceedings of the Technology of Object-Oriented Languages and Systems
SUAVE: Painless Extension For An Object-Oriented VHDL
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
A compositional approach to Statecharts semantics
A compositional approach to Statecharts semantics
Playing with Time: On the Specification and Execution of Time-Enriched LSCs
MASCOTS '02 Proceedings of the 10th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A unified approach to hardware verification through a heterogeneous logic of design diagrams
Formalizing the UML class diagram using object-Z
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
On the Modeling Timing Behavior of the System with UML(VR)
ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Model-driven automation for simulation-based functional verification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
An aspect-oriented, model-driven approach to functional hardware verification
Journal of Systems Architecture: the EUROMICRO Journal
Optimized temporal monitors for SystemC
Formal Methods in System Design
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The advent of the system-on-chip and intellectual property hardware design paradigms makes protocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally intended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the development of the language, an evaluation of the language's utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered.