Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CESC: a visual formalism for specification and verification of SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Automated Synthesis of Assertion Monitors using Visual Specifications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
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Interface standard specification documents are notoriously difficult to read and interpret consistently. The advent of the system-on-chip design paradigm compounds the problem as multiple vendors attempt to interpret the standard consistently. Monitors, while popular for formal and semiformal verification, do not offer a readable, high-level description. We propose using Live Sequence Charts to specify hardware standards using a recent Virtual Sockets Interface Alliance standard as a running example.