Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Using Live Sequence Charts for Hardware Protocol Specification and Compliance Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Assertion-Based Design
Scenario and Property Checking of Real-Time Systems Using a Synchronous Approach
ISORC '01 Proceedings of the Fourth International Symposium on Object-Oriented Real-Time Distributed Computing
Playing with Time: On the Specification and Execution of Time-Enriched LSCs
MASCOTS '02 Proceedings of the 10th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Automated Synthesis of Assertion Monitors using Visual Specifications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
| Hi-index | 0.00 |
Verification of present day SoCs is proving to be challenging due to complex interactions among various subcomponents and IPs, with multiple clock domains and diverse bus protocols. The quality of verification depends on the precision in specifying the interaction behaviors. We propose a visual specification language called CESC (Clocked Event Sequence Chart), designed to specify interaction scenarios in SoCs. CESC provides a unique mechanism for representating multiple clock domains, based upon which event occurrences and interactions among different subcomponents can be represented. CESC has a pictorial and textual syntax, and a formal semantics to enable rigorous analysis. The semantics is based on standard notions of partial ordering and timed event traces. CESC is useful in many ways in formalizing SoC verification flows, namely, formalization of verification scenarios, synthesis of protocol checkers and consistency checking of specification versus implementation. This paper describes an algorithm to translate CESC scenarios to protocol checkers used in SoC verification flow. A few examples from industrial designs are included to illustrate the applicability of this formalism in specifying bus transactions and properties of protocols.