Introduction to algorithms
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Using Live Sequence Charts for Hardware Protocol Specification and Compliance Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Assertion-Based Design
CESC: a visual formalism for specification and verification of SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
An assertion-based verification methodology for system-level design
Computers and Electrical Engineering
Multi-clock SVA synthesis without re-writing
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked Event Sequence Chart). CESC is a visual language designed for specifying system level interactions involving single and multiple clock domains. It has well-defined graphical and textual syntax and formal semantics based on synchronous language paradigm enabling formal analysis of specifications. In this paper we provide an overview of CESC language with few illustrative examples. The algorithm for automated synthesis of assertion monitors from CESC specifications is described. A few examples from standard bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of monitor synthesis algorithm.