Specification and verification of concurrent programs by A∀automata
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Specification and verification of VHDL-based system-level hardware designs
Specification and validation methods
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Semantics and verification of action diagrams with linear timing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Tamagotchis Need Not Die - Verification of STATEMENT Design
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient Decompositional Model Checking for Regular Timing Diagrams
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
The ICOS Synthesis Environment
FTRTFT '98 Proceedings of the 5th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A visual approach to validating system level designs
Proceedings of the 15th international symposium on System Synthesis
Visual Specifications for Modular Reasoning about Asynchronous Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
PathFinder: A Tool for Design Exploration
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Towards a User-Friendly Design and Verification Environment
SEW '02 Proceedings of the 27th Annual NASA Goddard Software Engineering Workshop (SEW-27'02)
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated Synthesis of Assertion Monitors using Visual Specifications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using visual specifications in verification of industrial automation controllers
EURASIP Journal on Embedded Systems - Embedded System Design in Intelligent Industrial Automation
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Model checking is an automated approach to the formM verification of hardware and software. To allow model checking tools to be used by the hardware or software designers themselves, instead of by verification experts, the tools should support specification methods that correspond closely to the common usage. For hardware systems, timing diagrams form such a commonly used and visually appealing specification method. In this paper, we introduce a class of synchronous timing diagrams with a syntax and a formal semantics that is close to the informal usage. We present an efficient, decompositional algorithm for model checking such timing diagrams. This algorithm has been implemented in a user-friendly tool called RTDT (the Regular Timing Diagram Translator). We have applied this tool to verify several properties of Lucent's PCI synthesizable core.