Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Symbolic Model Checking
Timing Diagrams: Formalization and Algorithmic Verification
Journal of Logic, Language and Information
Formal Hardware Verification - Methods and Systems in Comparison
Formal Hardware Verification - Methods and Systems in Comparison
An Automata Based Interpretation of Live Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Using a Visual Formalism for Design Verification in Industrial Environments
ACoS '98/VISUAL '98, AIN '97 Selected papers on Services and Visualization: Towards User-Friendly Design
Scenario-Based Monitoring and Testing of Real-Time UML Models
«UML» '01 Proceedings of the 4th International Conference on The Unified Modeling Language, Modeling Languages, Concepts, and Tools
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
From Live Sequence Charts to State Machines and Back: A Guided Tour
IEEE Transactions on Software Engineering
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This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual specification, as Live Sequence Charts (LSCs), of the properties to be checked. The LSCs are automatically translated into the input format for the SystemC-based checker engine, which indicates during simulation, if the property is fulfilled or produces a counter-example, if the property is violated. The entire process from the visual property specification to the checking is largely automated, which makes our approach accessible even for users which have not been trained in formal methods.