Handbook of theoretical computer science (vol. B)
Deciding properties of nonregular programs
SIAM Journal on Computing
Parametric real-time reasoning
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Specification and verification of VHDL-based system-level hardware designs
Specification and validation methods
Reversal-Bounded Multicounter Machines and Their Decision Problems
Journal of the ACM (JACM)
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
New Decidability Results Concerning Two-way Counter Machines and Applications
ICALP '93 Proceedings of the 20th International Colloquium on Automata, Languages and Programming
A Real-Time Interval Logic and Its Decision Procedure
Proceedings of the 13th Conference on Foundations of Software Technology and Theoretical Computer Science
Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Integrating Behavior and Timing in Executable Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Formal Specification of Real-time Systems
Formal Specification of Real-time Systems
A Graphical Interval Logic for Specifying Concurrent Systems
A Graphical Interval Logic for Specifying Concurrent Systems
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A unified approach to hardware verification through a heterogeneous logic of design diagrams
The Mathematical Theory of Context-Free Languages
The Mathematical Theory of Context-Free Languages
A visual approach to validating system level designs
Proceedings of the 15th international symposium on System Synthesis
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
PathFinder: A Tool for Design Exploration
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Using visual specifications in verification of industrial automation controllers
EURASIP Journal on Embedded Systems - Embedded System Design in Intelligent Industrial Automation
Temporal modalities for concisely capturing timing diagrams
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Timing diagrams are popular in hardware design. They have been formalized for use in reasoning tasks, such as computer-aided verification. These efforts have largely treated timing diagrams as interfaces to established notations for which verification is decidable; this has restricted timing diagrams to expressing only regular language properties. This paper presents a timing diagram logic capable of expressing certain context-free and context-sensitive properties. It shows that verification is decidable for properties expressible in this logic. More specifically, it shows that containment of ω-regular languages generated by Büchi automata in timing diagram languages is decidable. The result relies on a correlation between timing diagram and reversal bounded counter machine languages.