Using visual specifications in verification of industrial automation controllers

Authors:
Valeriy Vyatkin;Gustavo Bouzon
Affiliations:
Department of Electrical and Computer Engineering, University of Auckland, Auckland, New Zealand;Controle Soluções em Mecatrônica Ltda., Lages, Brazil
Venue:
EURASIP Journal on Embedded Systems - Embedded System Design in Intelligent Industrial Automation
Year:
2008

Citing 2
Cited 1

Timing Diagrams: Formalization and Algorithmic Verification

Journal of Logic, Language and Information
Model Checking Synchronous Timing Diagrams

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design

Formal Verification of Downtimeless System Evolution in Embedded Automation Controllers

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Modeling and Verification of Discrete Event Systems

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Abstract

This paper deals with further development of a graphical specification language resembling timing-diagrams and allowing specification of partially ordered events in input and output signals. The language specifically aims at application in modular modelling of industrial automation systems and their formal verification via model-checking. The graphical specifications are translated into a model which is connected with the original model under study.