Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
The complementation problem for Bu¨chi automata with applications to temporal logic
Theoretical Computer Science
Specification and verification of concurrent programs by A∀automata
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Specification and verification of VHDL-based system-level hardware designs
Specification and validation methods
Hardware synthesis from requirement specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Semantics and verification of action diagrams with linear timing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A Graph-Based Method for Timing Diagrams Representation and Verification
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proving System Properties by Means of Trigger-Graph and Petri Nets
EUROCAST '95 Selection of Papers from the Fifth International Workshop on Computer Aided Systems Theory
Bus Protocol Conversion: from Timing Diagrams to State Machines
EUROCAST '91 Proceedings of the A Selection of Papers from the Second International Workshop on Computer Aided Systems Theory
PROCOMET '94 Proceedings of the IFIP TC2/WG2.1/WG2.2/WG2.3 Working Conference on Programming Concepts, Methods and Calculi
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
A Visual Fomalism for Real-Time Requirement Specifications
ARTS '97 Proceedings of the 4th International AMAST Workshop on Real-Time Systems and Concurrent and Distributed Software: Transformation-Based Reactive Systems Development
A unified approach to hardware verification through a heterogeneous logic of design diagrams
A unified approach to hardware verification through a heterogeneous logic of design diagrams
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Visual Specifications for Modular Reasoning about Asynchronous Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Temporal modalities for concisely capturing timing diagrams
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Timing diagrams are widely used in industrial practice to express precedence and timing relationships amongst a collection of signals. This graphical notation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called Regular Timing Diagrams (RTD's). RTD's have a precise syntax, and a formal semantics that is simple and corresponds to common usage. Moreover, RTD's have an inherent compositional structure, which is exploited to construct an efficient algorithm for model checking a RTD with respect to a system description. The algorithm has time complexity that is linear in the system size and a small polynomial in the representation of the diagram. The algorithm can be easily used with symbolic (BDDbased) model checkers. We illustrate the workings of our algorithm with the verification of a simple master-slave system.